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Description
A real-time testing system consisting of a large-area array of 72 QDR II+ SRAMs (larger than 10-Gbit manufactured in 65 nm CMOS technology) was developed and assembled on the Tibetan Plateau at an altitude of 4,300 m. A new topological structure with 9 QDR II+ devices operating synchronously by a single FPGA was proposed and the signal integrity of the large-area high-speed QDR II+ SRAMs was solved. Under harsh natural radiation conditions, the complex and expensive system monitored a large number of devices in parallel for 153 days uninterruptedly. 43 soft errors including single bit upsets (SBUs), multiple-cell upsets (MCUs), and burst errors were observed, 77% of the observed errors in the DUT are SBU, while the MCU fraction is 23%. Surprisingly, incidence of single neutron can upset up to 9 cells. A SER value of 2356 FIT/Mb was obtained at the test site.
